RTL/Digital circuit design, synthesis, and simulation/verification.
FPGA synthesis, verification.
Chip integration, algorithm implementation, and interface design.
Generate test pattern.
Requirement:
Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 1 years of experience.
Familiar with ASIC Flow / EDA Tool (Synthesis DCG , Scan at-speed insertion, LEC , CLP , PrimeTime STA , PTPX , Low power flow implement). Experience in CAD Team is a plus.
Familiar with ASIC/FPGA Integration(ARM CPU architecture , AXI / AHB / VCI Bus arbiter , Clock tree scheme , ASIC / SOC Power optimization flow, Xilinx FPGA V7 Scale).
Familiar with high-speed NAND flash spec and control
