Job Description:

• Physical design, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, DRC/LVS to tapeout.

Requirement:

• Familiar with Synopsys/Cadence backend design flow.
• Hand on APR physical design from netlist to DRC/LVS tapeout experience is required.
• Experienced in hierarchical implementation, low power design flow, timing closure, IR drop analysis, crosstalk analysis.
• Familiar with TCL/Perl scripting and design automation.
• Experience in 65/55nm design is must, and 28/40nm or below design is a plus.