Job Description:

• Develop the NVMe Verification environment by Verilog / System Verilog
• Formal verification flow build-up and checking.
• Verification and debug the high speed interface.

Requirement:

• Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
• Familiar with high speed (PCIE, USB, MIPI, SATA) protocol and architecture
• Knowledge and design experience of design verification such as UVM and system Verilog / Verilog.